Abstract: The mainstream synthetic aperture radar (SAR) image target detection algorithms based on central processing unit (CPU) and graphics processing unit (GPU) have disadvantages such as large model size, high computational complexity, low parallelism, and high power consumption, and are not suitable for deployment on resource limited platforms such as satellites and unmanned aerial vehicles. A SAR image target detection accelerator based on field programmable gate array (FPGA) is designed in this paper, taking into account the board resources, power consumption, inference speed and accuracy. The network model adopted by the accelerator is an optimized YOLOv4-tiny architecture, which optimizes the data bit width with a 16-bit fixed-point quantization and adds dilated convolutions to replace standard convolutions, thereby reducing the network model and parameters for deployment on resource limited FPGA. In the implementation of FPGA convolutional layers, multiple loops unrolling and loop blocks parallelism methods are used to accelerate convolution operations. The experimental results show that the optimized algorithm achieved a throughput of 15.24 GOPS on FPGA, with a recognition speed of 256 ms per image, which is between CPU and GPU. However, due to the FPGA hardware power consumption of only 3.06 W, the energy efficiency ratios of the proposed algorithm reach 18.4 times and 7.3 times that of CPU and GPU respectively.