Abstract: A 3-stage Ka-band power amplifier (PA) is demonstrated in a 55nm RFSOI CMOS device technology. The output stage employs a cascode configuration to enhance gain, reverse isolation, and output power, while the two driver stages utilize common-source (CS) topology to reduce power consumption. Neutralization capacitor techniques are applied across all three stages to improve gain and stability. Transformer-based matching networks are implemented between stages and at the output, achieving efficient power transfer while minimizing component count and chip area. Within the 24-28 GHz frequency range, the design demonstrates a peak gain of 28.3 dB. The maximum saturated output power (Psat) and power-added efficiency (PAE) reach 19.8 dBm and 28.9% at 27 GHz, respectively. The output 1-dB compression point (OP1dB) and corresponding PAE achieve optimal values of 16.3 dBm and 15.9% at 26 GHz. The compact chip occupies an area of 0.8 mm × 0.38 mm.