Abstract: To meet the real-time and deterministic requirements of massive data transmission in modern radar signal processing, this paper proposes and implements a high-performance PCIe DMA data communication scheme based on the domestic Phytium multi-core processor architecture. Addressing the memory access characteristics of the domestic platform, the Contiguous Memory Allocator (CMA) is employed to resolve the reservation issues of large-scale physical contiguous memory, while a NUMA-affinity scheduling strategy is utilized to optimize cross-node memory access latency. The software adopts a modular design, constructing a closed-loop system that encompasses transceiver management, synchronous/asynchronous reception, and real-time Built-in Test (BIT) monitoring. Experimental results demonstrate that when processing six channels of high-speed optical fiber signals, the system throughput is more than doubled compared to the traditional XDMA driver mode, with single-channel transmission jitter reduced by over 15%, CPU utilization dropping from 85% to 8%, and the bit error rate reduced to the order of 1.0×10^-12, effectively resolving the real-time interaction bottleneck for high-bandwidth radar data on indigenous platforms.