Abstract: To meet the demands of high performance applications in modern radar, RASP architecture is presented in this paper. Through anomalistic microstructure and mixed reconfigurable strategy, the performance of parallel-pipeline compute improves in effect. With ping-pang processing method which conceals DDR read-write time, RASP also gives full play to the efficiency of computing resources. As a co-processor, RASP is tapped out and integrated in the DSP chip Huarui-2 with TSMC 40 nm. The test results demonstrate that 1 K FFT calculating only needs 2.57μs. The processing efficiency is as high as 42%. The performance is about 1.9~30 times and the efficiency is about 1.25~4 times as other FFT processors like NoC, MorphoSys, C6678, T4240, et al.