Abstract: In radar signal processing system using FPGA as the major processing chips, due to the low jump-row accessing rate of DDR, large-dimension matrix transposition often become the bottleneck of the system processing. This paper detailed analysis the access mechanism of DDR, and quantitatively analysis the composition of DDR access time, and presents a partitioning matrix transposition method to improve efficiency of matrix transposition. Using matrix partitioning technology, this method balances the access speed between DDR read and write during the matrix transposition process, thus improve the average efficiency of DDR access. Measurements data of matrix transposition efficiency through lab tests of DDR access are also provided to verify the validity of the method. The method has been applied successfully in engineering practices.