Abstract: SystemVerilog is a specialized language for FPGA verification, and its constrained random mechanism is the kernel to support FPGA random test. However, the SystemVerilog language only provides a constrained randomization mechanism for integral data types, which greatly limits the verification when floating-point random stimulus is needed. In this article, a floating-point constraint generator based on SystemVerilog is designed. It realizes the generation of constrained random floating-point number through a conversion mechanism, and thus extends the SystemVerilog constrained random mechanism to floating-point data types, which effectively expands the support range of SystemVerilog for constrained random test.