A Design and Implementation of Parallel FFT Based on ADRES

According to the SIMD(Single Instruction Multiple Data) characteristics of ADRES (Architecture for Dynamic Reconfigurable Embedded System,ADRES) processor, a parallel FFT algorithm based on SIMD was presented to improve the performance in this paper. Eight radix-4 butterflies were parallel calculated in each instruction cycle. At the same time, data shuffling and address reverse order were embedded in the vector butterfly calculation. These two methods both ensure the parallelism of vector computation and hide the time of FFT results′ order inversion. The SIMD FFT algorithm was implemented on ADRES processor and simulated results demonstrate that the calculation speed is about 1. 1~10 times as other FFT algorithms with the same scale of computed element.