Design of Ultra Large Points FFT Processor with Scalable Architecture

The high performance ultra large sequence fast Fourier transformation (FFT) processor for the synthetic aperture radar, remote sensing, and electronic countermeasure applications is presented in this paper. A scalable architecture is proposed which can dynamically adjust the FFT radices and points. The memory is divided to 16 banks which can be accessed by the conflict-free address. The input frame and output fame share the same memory, showing memory-efficient feature. The parallel pipeline arrangement is adopted by the FFT computation. When the high radices is adopted, the memory can be accessed with high parallelism and the parallel computation is realized, resulting in obvious real time advantage. The address is generated by the circular and shift register in every stage to guarantee the decimation distance of data fed to the butterfly unit. At the last stage, the circular and shift register is reversed to generate address, resulting in the same memory can be shared by the input and output data. The proposed design method is unified, efficient, general, and friendly for the implementation of the field programmable gate array and very large scale integration. The design will be benefited from the memory fabrication technique enhancement continuously.